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Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
24-10 Freescale Semiconductor
24.3.2.2 eDMA Error Status Register (EDMA_ESR)
The EDMA_ESR provides information about the last recorded channel error. Channel errors can be caused
by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority register
setting in fixed-arbitration mode) or an error termination to a bus master read or write cycle.
A configuration error is caused when the starting source or destination address, source or destination
offsets, minor loop byte count, and the transfer size represent an inconsistent state. The addresses and
offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a
multiple of the source and destination transfer sizes. All source reads and destination writes must be
configured to the natural boundary of the programmed transfer size respectively.
In fixed-arbitration mode, a configuration error is generated when any two channel priority levels are equal
and any channel is activated. The ERRCHN field is undefined for this type of error. All channel priority
levels must be unique before any service requests are made.
If a scatter-gather operation is enabled on channel completion, a configuration error is reported if the
scatter-gather address (DLAST_SGA) is not aligned on a 32-byte boundary. If minor loop channel linking
is enabled on channel completion, a configuration error is reported when the link is attempted if the
TCD.CITER.E_LINK bit is not equal to the TCD.BITER.E_LINK bit. All configuration error conditions
except scatter-gather and minor loop link error are reported as the channel is activated and assert an error
interrupt request if enabled. When properly enabled, a scatter-gather configuration error is reported when
the scatter-gather operation begins at major loop completion. A minor loop channel link configuration
error is reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is immediately stopped and the
appropriate bus error flag is set. In this case, the state of the channel’s transfer control descriptor is updated
by the DMA engine with the current source address, destination address, and minor loop byte count at the
point of the fault. If a bus error occurs on the last read prior to beginning the write sequence, the write is
executed using the data captured during the bus error. If a bus error occurs on the last write prior to
switching to the next read sequence, the read sequence is executed before the channel is terminated due to
the destination bus error.
A transfer may be cancelled by software via the EDMA_CR[CX] bit. When a cancel transfer request is
recognized, the eDMA engine stops processing the channel. The current read-write sequence is allowed to
finish. If the cancel occurs on the last read-write sequence of a major or minor loop, the cancel request is
discarded and the channel retires normally.
The error cancel transfer is the same as a cancel transfer except the DMAES register is updated with the
cancelled channel number and error cancel bit is set. The TCD of a cancelled channel has the source
address and destination address of the last transfer saved in the TCD. It is the responsibility of the user to
initialize the TCD again should the channel need to be restarted because the aforementioned fields have
been modified by the eDMA engine and no longer represent the original parameters. When a transfer is
cancelled via the error cancel transfer mechanism (setting the EDMA_CR[ECX]), the channel number is
loaded into the EDMA_ESR[ERRCHN] field and the EDMA_ESR[ECX] and EDMA_ESR[VLD] bits
are set. In addition, an error interrupt may be generated if enabled. Refer to
Section 24.3.2.14, eDMA Error
Register (EDMA_ERL).