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e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
13-6 Freescale Semiconductor
Memory load and store operations are provided for byte, halfword, word (32-bit), and doubleword data
with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of
data. These instructions can be pipelined to allow effective single cycle throughput. Load and store
multiple word instructions allow low overhead context save and restore operations. The load/store unit
contains a dedicated effective address adder to allow effective address generation to be optimized.
The condition register unit supports the condition register (CR) and condition register operations defined
by the Power Architecture embedded category. The condition register consists of eight 4-bit fields that
reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and
logical instructions, and provide a mechanism for testing and branching.
Vectored and auto-vectored interrupts are supported by the CPU. Vectored interrupt support is provided to
allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
The SPE APU supports vector instructions operating on 16- and 32-bit fixed-point data types, as well as
32-bit IEEE

754 single-precision floating-point formats, and supports single-precision floating-point
operations in a pipelined fashion. The 64-bit general-purpose register file is used for source and destination
operands, and there is a unified storage model for single-precision floating-point data types of 32-bits and
the normal integer type. Low latency fixed-point and floating-point add, subtract, multiply, divide,
compare, and conversion operations are provided, and most operations can be pipelined.
13.2 Core Registers and Programmer’s Model
This section describes the registers implemented in the e200z6 core. It includes an overview of registers
defined by the Power Architecture embedded category, highlighting differences in how these registers are
implemented in the e200z6 core, and provides a detailed description of core-specific registers. Full
descriptions of the architecture-defined register set are provided in the Power Architecture embedded
category.
The Power Architecture embedded category defines register-to-register operations for all computational
instructions. Source data for these instructions are accessed from the on-chip registers or are provided as
immediate values embedded in the opcode. The three-register instruction format allows specification of a
target register distinct from the two source registers, thus preserving the original data for use by other
instructions. Data is transferred between memory and registers with explicit load and store instructions
only.
e200z6 extends the general-purpose registers to 64-bits for supporting SPE APU operations. Power
Architecture instructions operate on the lower 32 bits of the GPRs only, and the upper 32 bits are
unaffected by these instructions. SPE vector instructions operate on the entire 64-bit register. The SPE
APU defines load and store instructions for transferring 64-bit values to/from memory.
Figure 13-2 and Figure 13-3 show the complete e200z6 register set. Figure 13-2 shows the registers that
are accessible while in supervisor mode, and Figure 13-3 shows the set of registers that are accessible
while in user mode. The number to the right of the special-purpose registers (SPRs) is the decimal number
used in the instruction syntax to access the register (for example, the integer exception register (XER) is
SPR 1).