NXP Semiconductors PXN2020, Справочное руководство, Страница: 173 / 1376

Frequency Modulated Phase-Locked Loop (FMPLL)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 7-11
7.4.2 PLL Off Mode
When PLL Off mode is selected, the PLL is turned off. Either the 16 MHz IRC must be selected as the
system clock, or the user must supply an external clock or crystal on the EXTAL pin and select that clock
source before entering PLL off mode. The selected clock is directly used to produce the various system
clocks. Refer to
PXN20 Microcontroller Data Sheet for external clock input requirements. In PLL Off
mode, the analog portion of the PLL is disabled, the frequency modulation capability is not available, and
no clocks are generated at the PLL output. The pre-divider is bypassed and has no effect on the system
clock frequency in PLL Off mode.
7.4.3 Normal Mode
When normal PLL mode is selected, the PLL is fully programmable. The PLL can synthesize frequencies
ranging from 48× to 148× the reference frequency of the output of the predivider. with or without
frequency modulation enabled. The post-divider is capable of reducing the PLL clock frequency without
forcing a re-lock. The PLL reference can be a crystal oscillator reference or an external clock reference.
This clock is divided by the pre-divider circuit to create the PLL reference clock.
7.4.3.1 PLL Lock Detection
The lock detect logic monitors the reference frequency and the PLL feedback frequency to determine when
frequency lock has been achieved. Phase lock is inferred by the frequency relationship, but is not
guaranteed. The PLL lock status is reflected in the LOCK status bit in the SYNSR. A sticky lock status
indication, LOCKS, is also provided.
The lock detect function uses two counters, which are clocked by the reference and PLL feedback
respectively. When the reference counter has counted N cycles, the feedback counter’s count is compared.
If the feedback counter has also counted N cycles, the process is repeated for N + K counts. Then if the
two counters’ counts match, the lock criteria is relaxed by one count and the system is notified that the
PLL has achieved frequency lock. After three successful compares, the tolerance is relaxed.
After lock has been detected, the lock circuitry continues to monitor the reference and feedback
frequencies using the alternate count and compare process. If the counters do not match at any comparison
time, then the LOCK status bit is cleared to indicate that the PLL has lost lock. At this point, the lock
criteria is tightened and the lock detect process is repeated.
The alternate count sequences prevent false lock detects due to frequency aliasing while the PLL tries to
lock. Alternating between a tight and relaxed lock criteria prevents the lock detect function from randomly
toggling between locked and not locked status due to phase sensitivities.
Figure 7-5 illustrates the
sequence for detecting locked and not-locked conditions.
When the frequency modulation is enabled, the loss of lock continues to function as described but with the
lock and loss of lock criteria reduced to ensure that false loss of lock conditions are not detected.
In PLL Off mode, the PLL cannot lock because the PLL is disabled.