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e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-5
13.1.3.5 L1 Cache Features
The features of the cache are as follows:
• 32 KB, 4- or 8-way set associative unified cache
• Copyback and writethrough support
• Eight-entry store buffer
• Push buffer
• Linefill buffer
• 32-bit address bus plus attributes and control
• Separate unidirectional 64-bit read data bus and 64-bit write data bus
• Supports cache line locking
• Supports way allocation
• Cache power usage can be minimized
13.1.3.6 BIU Features
The features of the e200z6 BIU are as follows:
• 32-bit address bus plus attributes and control
• Separate unidirectional 64-bit read data bus and 64-bit write data bus
• Overlapped, in-order accesses
13.1.4 Microarchitecture Summary
The e200z6 processor utilizes a seven stage pipeline for instruction execution. The instruction fetch 1,
instruction fetch 2, instruction decode/register file read, execute1, execute2/memory access1,
execute3/memory access2, and register writeback stages operate in an overlapped fashion, allowing single
clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit arithmetic unit (AU), a logic unit (LU), a 32-bit barrel shifter
(shifter), a mask-insertion unit (MIU), a condition register manipulation unit (CRU), a count-leading-zeros
unit (CLZ), a 32 x 32 hardware multiplier array, result feed-forward hardware, and support hardware for
division.
Most arithmetic and logical operations are executed in a single cycle with the exception of multiply, which
is implemented with a pipelined hardware array, and the divide instructions. A count-leading-zeros unit
operates in a single clock cycle.
The instruction unit contains a PC incrementer and a dedicated branch address adder to minimize delays
during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions
into the execution pipeline. Branch target prefetching is performed to accelerate taken branches.
Prefetched instructions are placed into an instruction buffer capable of holding six sequential instructions.
Branch target addresses are calculated in parallel with branch instruction decode, resulting in execution
time of three clocks. Conditional branches which are not taken execute in a single clock. Branches with
successful lookahead and target prefetching have an effective execution time of one clock.