NXP Semiconductors PXN2020, Справочное руководство, Страница: 353 / 1376

Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 12-27
12.4 Functional Description
12.4.1 Flash User Mode
In user mode the flash module can be read and written (register writes and interlock writes), programmed
or erased. The following sub-sections define all actions that can be performed in user mode.
12.4.1.1 Flash Read and Write
The default state of the flash module is read. The main and shadow address space can be read only in the
read state. The module configuration register (MCR) is always available for read. The flash module enters
the read state on reset. The flash module is in the read state under four sets of conditions:
• The read state is active when the module is enabled.
Offset FLASH_REG 0x0054 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MISR[127:96]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-20. User Multiple Input Signature Register 3 (UM3)
Offset FLASH_REG 0x0058 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MISR[143:128]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-21. User Multiple Input Signature Register 4 (UM4)
Table 12-19. UMn Field Descriptions
Field Description
MISR Multiple Input Signature Register bits. The MISR bitfields accumulate a signature from an array integrity event. The
MISR captures all data fields, as well as ECC fields, and the read transfer error signal. The MISR can be seeded to
any value by writing the MISR registers.
The MISR register provides a means to calculate a MISR during Array Integrity operations.
The MISR can be represented by the following polynomial:
x
145
+ x
6
+ x
5
+ x
1
+ 1
The MISR is calculated by taking the previous MISR value and then “exclusive ORing” the new data. In addition the
most significant bit (in this case it is MISR[144]), is then “exclusive ORed” into input of MISR[6], MISR[5], MISR[1],
and MISR[0]. The result of the “exclusive OR” is shifted left on each read.
The MISR register is used in Array Integrity operations.
If during address sequencing, reads extend into an invalid address location (i.e. greater than the maximum address
for a given array size) or locked/un-selected blocks. Reads are still executed to the array, but the results from the
array read are not deterministic. In this instance, the MISR registers is not re-calculated, and the previous value is
retained.