NXP Semiconductors LPC800, Руководство пользователя

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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 17 of 313
NXP Semiconductors
UM10601
Chapter 4: LPC800 System configuration (SYSCON)
4.5.3 Configuration of reduced power-modes
The system control block configures analog blocks that can remain running in the reduced
power modes (the BOD and the watchdog oscillator for safe operation) and enables
various interrupts to wake up the chip when the internal clocks are shut down in
Deep-sleep and Power-down modes. For details, see the following registers:
Section 4.6.32 “Power configuration register”
Section 4.6.29 “Start logic 1 interrupt wake-up enable register”
4.5.4 Reset and interrupt control
The peripheral reset control register in the system control register allows to assert and
release individual peripheral resets. See
Table 7 .
Up to eight external pin interrupts can be assigned to any digital pin in the system control
block (see
Section 4.6.27 “Pin interrupt select registers” ).
4.6 Register description
All system control block registers reside on word address boundaries. Details of the
registers appear in the description of each function.
Reset values describe the content of the registers after the boot loader has executed.
All address offsets not shown in Table 5 are reserved and should not be written.
Table 5. Register overview: System configuration (base address 0x4004 8000)
Name Access Offset Description Reset value Reference
SYSMEMREMAP R/W 0x000 System memory remap 0x2 Table 6
PRESETCTRL R/W 0x004 Peripheral reset control 0x0000 1FFF Table 7
SYSPLLCTRL R/W 0x008 System PLL control 0 Table 8
SYSPLLSTAT R 0x00C System PLL status 0 Table 9
- - 0x010 Reserved - -
- - 0x014 Reserved - -
SYSOSCCTRL R/W 0x020 System oscillator control 0x000 Table 10
WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x0A0 Table 11
- - 0x028 Reserved - -
- - 0x02C Reserved - -
SYSRSTSTAT R/W 0x030 System reset status register 0 Table 12
SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0 Table 13
SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0 Table 14
MAINCLKSEL R/W 0x070 Main clock source select 0 Table 15
MAINCLKUEN R/W 0x074 Main clock source update enable 0 Table 16
SYSAHBCLKDIV R/W 0x078 System clock divider 1 Table 17
SYSAHBCLKCTRL R/W 0x080 System clock control 0x1F Table 18
UARTCLKDIV R/W 0x094 USART clock divider 0 Table 19
- - 0x098 Reserved -
-