DRAFT
DRAFT DRAFT DR
DRAFT DRAFT DRAFT
D
RAF
DRAFT DRAFT DRA
FT D
AFT D
DRA
FT DRAFT DRAFT
DRAFT
DRA
UM10601
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© NXP B.V. 2012. All rights reserved.
Preliminary user manual
Rev. 1.0 — 7 November 2012
186 of 313
NXP Semiconductors
UM10601
Chapter 16: LPC800 I2C-bus interface
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Table 181 “Master Data register (MSTDAT, address 0x4005 0028) bit description”
•
Slave function registers:
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Table 182 “Slave Control register (SLVCTL, address 0x4005 0040) bit description”
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Table 182 “Slave Control register (SLVCTL, address 0x4005 0040) bit description”
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Table 185 “Slave address Qualifier 0 register (SLVQUAL0, address 0x4005 0058)
bit description”
•
Monitor function register: