NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
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Cortex
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-M0 Microcontroller
Aug, 2018
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The received FIFO buffer is also an 8-layer depth, 32-bit wide, first-in, first-out register buffer. The
receive control logic will store the received data to this buffer. The FIFO buffer data can be read
from SPI_RX0 register by software. There are FIFO related status bits, like RX_EMPTY and
RX_FULL, to indicate the current status of FIFO buffer.
In FIFO mode, the transmitting and receiving threshold can be set through software by setting the
TX_THRESHOLD and RX_THRESHOLD settings. When the count of valid data stored in transmit
FIFO buffer is less than or equal to TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1.
When the count of valid data stored in receive FIFO buffer is larger than RX_THRESHOLD
setting, the RX_INTSTS bit will be set to 1.
In FIFO mode, 8 data can be written to the SPI transmit FIFO buffer by software in advance.
When the SPI controller operates with FIFO mode, the GO_BUSY bit of SPI_CNTRL register will
be controlled by hardware, and the content of SPI_CNTRL register should not be modified by
software unless the FIFO bit is cleared to disable FIFO mode.
Receive buffer n
Receive buffer 2
Transmit buffer n
Transmit buffer 2
Receive buffer 1
Transmit buffer 1
SPIn_MOSI0 Pin in Master Mode
or
SPIn_MISO0 Pin in Slave Mode
SPIn_MISO0 Pin in Master Mode
or
SPIn_MOSI0 Pin in Slave Mode
SPI_TX Buffer
Transmit Buffer 0
Receive Buffer 0
SPI_RX Buffer
APB
Write
Read
1
2
n
1
2
n
Figure 6.15-10 FIFO Mode Block Diagram
In Master mode, when the FIFO bit is set to 1 and the first datum is written to the SPI_TX0
register, the TX_EMPTY flag will be cleared to 0. The transmission immediately starts as long as
the transmit FIFO buffer is not empty. User can write the next data into SPI_TX0 register
immediately. The SPI controller will insert a suspend interval between two successive
transactions in FIFO mode and the period of suspend interval is decided by the setting of
SP_CYCLE (SPI_CNTRL [15:12]). User can write data into SPI_TX0 register as long as the
TX_FULL flag is 0.
The subsequent transactions will be triggered automatically if the transmitted data are updated in
time. If the SPI_TX0 register does not be updated after all data transfer are done, the transfer will
stop.
In Master mode, during receiving operation, the serial data are received from SPIn_MISO0/1 pin
and stored to receive FIFO buffer. The RX_EMPTY flag will be cleared to 0 while the receive
FIFO buffer contains unread data. The received data can be read by software from SPI_RX0
register as long as the RX_EMPTY flag is 0. If the receive FIFO buffer contains 8 unread data, the
