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Index
I-2
ni.com
B
block diagram of NI PXI-4204, 3-2
C
external calibration, 3-24
loading calibration constants, 3-23
pre-calibration errors, A-4
self-calibration, 3-23
specifications, A-4
channel properties, configuring, 3-14
in application development (table), 3-14
in LabVIEW, 3-17
chassis ground screw, D-1
PXI trigger bus
clocks, PXI, 3-9
DAQ timing conventions
See
high CMV connection
common questions, D-1
common-mode rejection (CMR), effective, 3-6
common-mode rejection ratio (CMRR), 3-5
configuring
in LabVIEW, 3-17
NI-DAQmx properties (table), 3-14
conventions used in the manual,
D
DAQ Assistant, 3-13
DAQ timing conventions, B-2
AI CONV CLK
description, B-7
input signal timing (figure), B-7
output signal timing (figure), B-8
overview (table), 3-11
AI HOLD COMPLETE
description, B-9
signal timing (figure), B-10
AI PAUSE TRIG
description, B-8
overview (table), 3-11
AI REF TRIG
description, B-4
input signal timing (figure), B-4
output signal timing (figure), B-5
overview (table), 3-10
AI SAMP CLK
description, B-5
input signal timing (figure), B-6
output signal timing (figure), B-6
overview (table), 3-11
AI SAMPLE CLK TIMEBASE
description, B-9
overview (table), 3-11
signal timing (figure), B-9
AI START TRIG
description, B-2
input signal timing (figure), B-3
overview (table), 3-10
posttriggered sequence (figure), B-2
pretriggered sequence (figure), B-2
DAQmx channel property node, using in
DAQ-STC timing controller, 3-7
developing applications.
See
application
development
device and PXI clocks, 3-9
differential signals, 3-4
digital trigger specifications, A-5
Divide-by-Ten Attenuator (table), 3-3
documentation
application development, 3-22
National Instruments documentation, 1-2