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Appendix B
Timing Signal Information
©
National Instruments Corporation
B-9
AI SAMPLE CLK TIMEBASE Signal
PFI0, PXI_Trig<0..5>, or PXI Star can externally input the
AI SAMPLE CLK TIMEBASE signal, which is not available as an output
on the I/O connector. The onboard scan interval (SI) counter uses
AI SAMPLE CLK TIMEBASE as a clock to time the generation of the
AI SAMP CLK signal. Configure the pin you select as the source for
AI SAMPLE CLK TIMEBASE in level-detection mode. Configure
the polarity selection for the pin for either active high or active low.
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 23 ns high or low. There is no minimum frequency.
Either the 20 MHz or 100 kHz internal timebase generates
AI SAMPLE CLK TIMEBASE unless you select an external source.
Figure B-11 shows the timing requirements for
AI SAMPLE CLK TIMEBASE.
Figure B-11.
AI SAMPLE CLK TIMEBASE Signal Timing
AI HOLD COMPLETE Signal
AI HOLD COMPLETE is an output-only signal that generates a pulse with
the leading edge occurring approximately 50 to 100 ns after an A/D
conversion begins. The polarity of this output is software configurable, but
the polarity is typically configured so that a low-to-high leading edge can
clock external analog input multiplexers indicating when the input signal
has been sampled and can be removed. This signal has a 400 to 500 ns pulse
width and is software enabled. Figure B-12
shows the timing for
AI HOLD COMPLETE.
Note
The polarity of AI HOLD COMPLETE is not software selectable when
programmed using NI-DAQmx. It is a positive polarity pulse.
t
w
= 23 ns minimum
t
p
= 50 ns minimum
t
p
t
w
t
w