CHAPTER 2 PIN FUNCTIONS
User’s Manual U14272EJ3V0UM
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Signal name
I/O
Description of function
SYSDIR
Note
Output
Data bus isolation buffer direction control. This signal is valid only when ROM, ISA,
or CompactFlash accesses are enabled.
This becomes low level during ROM, ISA, or CompactFlash read cycle, or becomes
high level during ROM, ISA, or CompactFlash write cycle.
SYSEN#
Note
Output
Data bus isolation buffer enable. This signal is valid only when ROM, ISA, or
CompactFlash accesses are enabled.
This becomes active during ROM or ISA cycle.
SDCS(1:0)#/RAS(1:0)#
Output
SDRAM chip select for bank 0 and bank 1 or EDO DRAM row address strobes.
CAS#
Output
SDRAM column address strobe. Leave unconnected when using EDO DRAM.
SDRAS#
Output
SDRAM row address strobe. Leave unconnected when using EDO DRAM.
UDQM/UCAS#
Output
SDRAM upper byte enable or EDO DRAM upper byte column address strobe.
LDQM/LCAS#
Output
SDRAM lower byte enable or EDO DRAM lower byte column address strobe.
SDCLK
Output
SDRAM operating clock.
CLKEN
Output
SDRAM clock enable output (CKE).
ROMCS3#
Output
ROM chip select output for bank 3.
ROMCS2#/GPIO24
I/O
ROM chip select output for bank 2, or general-purpose I/O.
ROMCS1#/GPIO23
I/O
ROM chip select output for bank 1, or general-purpose I/O.
ROMCS0#/GPIO22
I/O
ROM chip select output for bank 0, or general-purpose I/O.
MEMRD#
Output
Memory read signal for ROM and system bus.
MEMWR#
Output
Memory write signal for ROM, DRAM and system bus.
Note The SYSEN# and SYSDIR signals control a buffer which is used to isolate SDRAM data bus from the bus of
other low speed devices. By isolating the high-speed data bus of SDRAM, the load of the data bus between
the V
R
4181 and SDRAM is reduced.
When the EXBUFFEN bit of the XISACTL register is cleared to 0, the SYSEN# and SYSDIR signals start their
operation. These signals keep low level until EXBUFFEN bit is cleared to 0 after a reset.
When an isolation buffer is used, SYSEN# and SYSDIR signals function as follows;
SYSEN#
SYSDIR
Bus operation
0
0
External ISA, CompactFlash, or ROM read cycle
0
1
External ISA, CompactFlash, or flash memory mode write cycle
1
Don’t care
External Buffer Disable
DRAM read/write cycle or Hibernate mode
Содержание VR4181 mPD30181
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