NEC VR4181 mPD30181, Руководство пользователя

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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU)
User’s Manual U14272EJ3V0UM
262
13.3.11 GPINTSTAT (0x0B00 0314)
Bit 15 14 13 12 11 10 9 8
Name GISTS15 GISTS14 GISTS13 GISTS12 GISTS11 GISTS10 GISTS9 GISTS8
R/W R/W R/W R/W R/W R/W R/W R/W R/W
RTCRST 0 0 0 0 0 0 0 0
Other resets
Note Note Note Note Note Note Note Note
Bit 7 6 5 4 3 2 1 0
Name GISTS7 GISTS6 GISTS5 GISTS4 GISTS3 GISTS2 GISTS1 GISTS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
RTCRST 0 0 0 0 0 0 0 0
Other resets Note Note Note Note Note Note Note Note
Bit Name Function
15 to 0 GISTS(15:0) GPIO interrupt request status. There is a one-to-one correspondence between
these bits and GPIO pins. When a GPIO pin is defined as a general-purpose
input, these bits reflect the interrupt request status as follows:
0 : No Interrupt request pending
1 : Interrupt request pending
Note Holds the value before reset
Interrupt request pending status is reflected regardless of the setting of the interrupt mask bits. Therefore, the
status of an interrupt request can be returned as pending when this register is read even though the interrupt is
masked.
When a GPIO interrupt request is defined as an edge triggered type, the interrupt request is cleared by writing 1 to
the corresponding bit of this register. For example, if GPIO11 is defined as an edge triggered interrupt request input,
an interrupt request generated by this pin would be cleared by writing 1 to the bit 11 of this register.