NEC VR4181 mPD30181, Руководство пользователя

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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU)
User’s Manual U14272EJ3V0UM
263
13.3.12 GPHIBSTH (0x0B00 0316)
Bit 15 14 13 12 11 10 9 8
Name GPHST31 GPHST30 GPHST29 GPHST28 GPHST27 GPHST26 GPHST25 GPHST24
R/W R/W R/W R/W R/W R/W R/W R/W R/W
RTCRST 0 0 0 0 0 0 0 0
Other resets
Note Note Note Note Note Note Note Note
Bit 7 6 5 4 3 2 1 0
Name GPHST23 GPHST22 GPHST21 GPHST20 GPHST19 GPHST18 GPHST17 GPHST16
R/W R/W R/W R/W R/W R/W R/W R/W R/W
RTCRST 0 0 0 0 0 0 0 0
Other resets Note Note Note Note Note Note Note Note
Bit Name Function
15 to 0 GPHST(31:16) GPIO Hibernate pin state control. There is a one-to-one correspondence between
these bits and GPIO pins. These bits determine the state of GPIO(31:16) pins
during Hibernate mode as follows:
0 : Output pin is in high impedance
Input pin is ignored during Hibernate mode
1 : Output pin remains actively driven
Input pin is monitored during Hibernate mode
Note Holds the value before reset
Caution GPIO29 pin (DCD1#) can be input at high level and monitored during Hibernate mode and
therefore the GPHST29 bit can be set to 1. The GPHST bits for all other GPIO pins configured as
inputs should be reset to 0.