CHAPTER 1 INTRODUCTION
User’s Manual U14272EJ3V0UM
36
(1) CPU
The CPU has hardware resources to process an integer instruction. They are the 64-bit register file, 64-bit
integer data path, and multiply-and-accumulate operation unit.
(2) Coprocessor 0 (CP0)
The CP0 incorporates a memory management unit (MMU) and exception handling function. MMU checks
whether there is an access between different memory segments (user, supervisor, and kernel) by executing
address translation. The translation lookaside buffer (TLB) translates virtual addresses to physical addresses.
(3) Instruction cache
The instruction cache employs direct mapping, virtual index, and physical tag. Its capacity is 4 KB.
(4) Data cache
The data cache employs direct mapping, virtual index, physical tag, and writeback. Its capacity is 4 KB.
(5) CPU bus interface
The CPU bus interface controls data transmission/reception between the V
R
4110 core and the MBA Host Bridge.
This interface consists of two 32-bit multiplexed address/data buses (one is for input, and another is for output),
clock signal, and control signals such as interrupt requests.
(6) Clock generator
The following clock inputs are oscillated and supplied to internal units.
•
32.768 kHz clock for RTC unit
Crystal resonator input oscillated via an internal oscillator and supplied to the RTC unit.
•
18.432 MHz clock for serial interface and the V
R
4181’s reference operating clock
Crystal resonator input oscillated via an internal oscillator, and then multiplied by phase-locked loop (PLL) to
generate a pipeline clock (PClock). The internal bus clock (TClock) is generated from PClock and supplied to
peripheral units.
Содержание VR4181 mPD30181
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