NEC V850/SC1, Руководство пользователя

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CHAPTER 20 ELECTRICAL SPECIFICATIONS
694
User’s Manual U15109EJ3V0UD
(4) Bus timing
(a) Clock asynchronous (T
A
= –40 to +85°C, V
DD
= 4.0 to 5.5 V, PORTV
DD
= 4.0 to 5.5 V)
Parameter Symbol Conditions MIN. MAX. Unit
Address setup time (to ASTB
↓
) <10> t
SAST
0.5T – 20 ns
Address hold time (from ASTB
↓
) <11> t
HSTA
0.5T – 15 ns
Delay time from DSTB
↓
to address float <12> t
FDA
0 ns
Data input setup time from address <13> t
SAID
(2 + n)T – 40 ns
Data input setup time from DSTB
↓
<14> t
SDID
(1 + n)T – 40 ns
Data input setup time from ASTB
↓
<15> t
SASID
(1.5 + n)T – 51 ns
Delay time from ASTB
↓
to DSTB
↓
<16> t
DSTD
0.5T – 15 ns
Data input hold time (from DSTB
↑
) <17> t
HDID
0 ns
Address output time from DSTB
↑
<18> t
DDA
(1 + i)T – 15 ns
Delay time from DSTB
↑
to ASTB
↑
<19> t
DDST1
0.5T – 15 ns
Delay time from DSTB
↑
to ASTB
↓
<20> t
DDST2
(1.5 + i)T – 15 ns
DSTB low-level width <21> t
WDL
(1 + n)T – 22 ns
ASTB high-level width <22> t
WSTH
T – 15 ns
Data output time from DSTB
↓
<23> t
DDOD
10 ns
Data output setup time (to DSTB
↑
) <24> t
SODD
(1 + n)T – 25 ns
Data output hold time (from DSTB
↑
) <25> t
HDOD
T – 20 ns
<26> t
SAWT1
n
≥
1 1.5T – 40 ns WAIT setup time (to address)
<27> t
SAWT2
(1.5 + n)T – 40 ns
<28> t
HAWT1
n
≥
1 (0.5 + n)T ns WAIT hold time (from address)
<29> t
HAWT2
(1.5 + n)T ns
<30> t
SSTWT1
n
≥
1 T – 32 ns WAIT setup time (to ASTB
↓
)
<31> t
SSTWT2
(1 + n)T – 32 ns
<32> t
HSTWT1
n
≥
1 nT ns WAIT hold time (from ASTB
↓
)
<33> t
HSTWT2
(1 + n)T ns
HLDRQ high-level width <34> t
WHQH
T + 10 ns
HLDAK low-level width <35> t
WHAL
T – 15 ns
Delay time from HLDAK
↑
to bus output <36> t
DHAC
– 11 ns
Delay time from HLDRQ
↓
to HLDAK
↓
<37> t
DHQHA1
1.5T (2n + 7.5)T + 25 ns
Delay time from HLDRQ
↑
to HLDAK
↑
<38> t
DHQHA2
0.5T 1.5T + 25 ns
Remarks 1. T: 1/f
CPU
(f
CPU
: CPU clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. i: Number of idle cycles inserted in the bus cycle.
4. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input
from X1.