Chapter 6
Digital I/O
X Series User Manual
6-6
ni.com
DI Sample Clock Signal
The device
u
ses the DI Sample Clock (di/SampleClock) signal to sample the
Port 0 terminals and store the res
u
lt in the DI waveform acq
u
isition FIFO.
Yo
u
can specify an internal or external so
u
rce for DI Sample Clock. Yo
u
also can specify whether the meas
u
rement sample begins on the rising edge
or falling edge of DI Sample Clock.
If the DAQ device receives a DI Sample Clock when the FIFO is f
u
ll,
it reports an overflow error to the host software.
Using an Internal Source
To
u
se DI Sample Clock with an internal so
u
rce, specify the signal so
u
rce
and the polarity of the signal. The so
u
rce can be any of the following
signals:
•
DI Sample Clock (di/SampleClock)
•
DO Sample Clock (do/SampleClock)
•
AI Sample Clock (ai/SampleClock)
•
AI Convert Clock (ai/ConvertClock)
•
AO Sample Clock (ao/SampleClock)
•
Co
u
nter
n
Sample Clock
•
Co
u
nter
n
Internal O
u
tp
u
t
•
Freq
u
ency O
u
tp
u
t
•
DI Change Detection o
u
tp
u
t
Several other internal signals can be ro
u
ted to DI Sample Clock thro
u
gh
internal ro
u
tes. Refer to
Device Routing in MAX
in the
NI-DAQmx Help
or
the
LabVIEW Help
for more information.
Using an External Source
Yo
u
can ro
u
te any of the following signals as DI Sample Clock:
•
PFI <0..15>
•
RTSI <0..7>
•
PXI_STAR
•
PXIe-DSTAR<A,B>
•
Analog Comparison Event (an analog trigger)
Yo
u
can sample data on the rising or falling edge of DI Sample Clock.
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