Chapter 9
Digital Routing and Clock Generation
X Series User Manual
9-8
ni.com
PXI and PXI Express Clock and Trigger Signals
PXI and PXI Express clock and trigger signals are only available on
PXI Express devices.
PXIe_CLK100
PXIe_CLK100 is a common low-skew 100 MHz reference clock for
synchronization of m
u
ltiple mod
u
les in a PXI Express meas
u
rement or
control system. The PXIe backplane is responsible for generating
PXIe_CLK100 independently to each peripheral slot in a PXI Express
chassis. For more information, refer to the
PXI Express Specification
at
www.pxi
s
a.org
.
PXIe_SYNC100
PXIe_SYNC100 is a common low-skew 10 MHz reference clock with a
10% d
u
ty cycle for synchronization of m
u
ltiple mod
u
les in a PXI Express
meas
u
rement or control system. This signal is
u
sed to acc
u
rately
synchronize mod
u
les
u
sing PXIe_CLK100 along with those
u
sing
PXI_CLK10. The PXI Express backplane is responsible for generating
PXIe_SYNC100 independently to each peripheral slot in a PXI Express
chassis. For more information, refer to the
PXI Express Specification
at
www.pxi
s
a.org
.
PXI_CLK10
PXI_CLK10 is a common low-skew 10 MHz reference clock for
synchronization of m
u
ltiple mod
u
les in a PXI meas
u
rement or control
system. The PXI backplane is responsible for generating PXI_CLK10
independently to each peripheral slot in a PXI chassis.
Note
PXI_CLK10 cannot be
u
sed as a reference clock for X Series devices.
PXI Triggers
A PXI chassis provides eight b
u
sed trigger lines to each mod
u
le in a
system. Triggers may be passed from one mod
u
le to another, allowing
precisely timed responses to asynchrono
u
s external events that are being
monitored or controlled. Triggers can be
u
sed to synchronize the operation
of several different PXI peripheral mod
u
les.
On X Series devices, the eight PXI trigger signals are synonymo
u
s with
RTSI <0..7>.
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