Chapter 9
Digital Routing and Clock Generation
X Series User Manual
9-2
ni.com
100 MHz Timebase
The 100 MHz Timebase can be
u
sed as the timebase for all internal
s
u
bsystems.
The 100 MHz Timebase is generated from the following so
u
rces:
•
Onboard oscillator
•
External signal (by
u
sing the external reference clock)
20 MHz Timebase
The 20 MHz Timebase can be
u
sed to generate many of the AI and AO
timing signals.The 20 MHz Timebase also can be
u
sed as the So
u
rce inp
u
t
to the 32-bit general-p
u
rpose co
u
nter/timers.
The 20 MHz Timebase is generated by dividing down the 100 MHz
Timebase.
100 kHz Timebase
The 100 kHz Timebase can be
u
sed to generate many of the AI and AO
timing signals. The 100 kHz Timebase also can be
u
sed as the So
u
rce inp
u
t
to the 32-bit general-p
u
rpose co
u
nter/timers.
The 100 kHz Timebase is generated by dividing down the 20 MHz
Timebase by 200.
External Reference Clock
The external reference clock can be
u
sed as a so
u
rce for the internal
timebases (100 MHz Timebase, 20 MHz Timebase, and 100 kHz
Timebase) on an X Series device. By
u
sing the external reference clock,
yo
u
can synchronize the internal timebases to an external clock.
The following signals can be ro
u
ted to drive the external reference clock:
•
RTSI <0..7>
•
PFI <0..15>
•
PXIe_CLK100
•
PXI_STAR
•
PXIe-DSTAR<A,B>
The external reference clock is an inp
u
t to a Phase-Lock Loop (PLL). The
PLL generates the internal timebases.
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