National Instruments DAQ X Series, Руководство пользователя

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Chapter 7 Counters
© National Instruments 7-5 X Series User Manual
Buffered (Sample Clock) Edge Counting
With b u ffered edge co u nting (edge co u nting u sing a sample clock), the
co u nter co u nts the n u mber of edges on the So u rce inp u t after the co u nter is
armed. The val u e of the co u nter is sampled on each active edge of a sample
clock and stored in the FIFO. A DMA controller transfers the sampled
val
u es to host memory.
The co u nt val u es ret u rned are the c u m u lative co u nts since the co u nter
armed event. That is, the sample clock does not reset the co u nter.
Yo u can config u re the co u nter to sample on the rising or falling edge of the
sample clock.
Fig u re 7-4 shows an example of b u ffered edge co u nting. Notice that
co u nting begins when the co u nter is armed, which occ u rs before the
first active edge on Sample Clock.
Figure 7-4. Buffered (Sample Clock) Edge Counting
Controlling the Direction of Counting
In edge co u nting applications, the co u nter can co u nt u p or down. Yo u can
config u re the co u nter to do the following:
• Always co u nt u p
• Always co u nt down
• Co u nt u p when the Co u nter 0 B inp u t is high; co u nt down when it
is low
For information abo u t connecting co u nter signals, refer to the Default
Counter/Timer Pinouts section.
3
6
3
Co u nter Armed
S OURCE
Sa mple Clock
( Sa mple on Ri s ing Edge)
Co u nter V a l u e
B u ffer
1 0 7 6 3 4 5 2
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