Hitachi H8S/2215 Series, Руководство по оборудованию

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Rev. 3.0, 10/02, page xlvi of lviii
Figure 7.16 Example of Short Address Mode Transfer .............................................................. 182
Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer........................................... 183
Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer .......................................... 183
Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer........................... 184
Figure 7.20 Example of
DREQ
Level Activated Normal Mode Transfer .................................. 185
Figure 7.21 Example of
DREQ
Level Activated Block Transfer Mode Transfer....................... 186
Figure 7.22 Example of Multi-Channel Transfer........................................................................ 187
Figure 7.23 Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt ..................................................................................................... 188
Figure 7.24 Example of Procedure for Forcibly Terminating DMAC Operation ....................... 189
Figure 7.25 Example of Procedure for Clearing Full Address Mode.......................................... 190
Figure 7.26 Block Diagram of Transfer End/Transfer Break Interrupt....................................... 191
Figure 7.27 DMAC Register Update Timing.............................................................................. 192
Figure 7.28 Contention between DMAC Register Update and CPU Read ................................. 193
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ........................................................................................... 196
Figure 8.2 Block Diagram of DTC Activation Source Control ................................................ 201
Figure 8.3 Correspondence between DTC Vector Address and Register Information ............. 202
Figure 8.4 Correspondence between DTC Vector Address and Register Information ............. 203
Figure 8.5 Flowchart of DTC Operation................................................................................... 205
Figure 8.6 Memory Mapping in Normal Mode ........................................................................ 207
Figure 8.7 Memory Mapping in Repeat Mode.......................................................................... 208
Figure 8.8 Memory Mapping in Block Transfer Mode............................................................. 209
Figure 8.9 Chain Transfer Memory Map .................................................................................. 210
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode).................... 211
Figure 8.11 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) ..................................... 212
Figure 8.12 DTC Operation Timing (Example of Chain Transfer)............................................. 212
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1 Block Diagram of TPU............................................................................................ 264
Figure 10.2 16-Bit Register Access Operation [Bus Master
↔
TCNT (16 Bits)] ...................... 291
Figure 10.3 8-Bit Register Access Operation [Bus Master
↔
TCR (Upper 8 Bits)].................. 291
Figure 10.4 8-Bit Register Access Operation [Bus Master
↔
TMDR (Lower 8 Bits)].............. 292
Figure 10.5 8-Bit Register Access Operation [Bus Master
↔
TCR and TMDR (16 Bits)]........ 292
Figure 10.6 Example of Counter Operation Setting Procedure................................................... 293
Figure 10.7 Free-Running Counter Operation ............................................................................ 294
Figure 10.8 Periodic Counter Operation ..................................................................................... 294
Figure 10.9 Example of Setting Procedure for Waveform Output by Compare Match .............. 295
Figure 10.10 Example of 0 Output/1 Output Operation.............................................................. 295
Figure 10.11 Example of Toggle Output Operation.................................................................... 296
Figure 10.12 Example of Input Capture Operation Setting Procedure........................................ 296
Figure 10.13 Example of Input Capture Operation ..................................................................... 297