Rev. 3.0, 10/02, page 324 of 686
Input capture
signal
Write signal
Address
φ
TCNT
Buffer register write cycle
T1
T2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 10.51 Contention between Buffer Register Write and Input Capture
Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and
counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing
takes precedence. Figure 10.52 shows the operation timing when a TGR compare match is
specified as the clearing source, and H'FFFF is set in TGR.
Counter
clear signal
TCNT input
clock
φ
TCNT
TGF
Disabled
TCFV
H'FFFF
H'0000
Figure 10.52 Contention between Overflow and Counter Clearing
Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-
count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write
takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.53 shows the operation
timing when there is contention between TCNT write and overflow.
Содержание H8S/2215 Series
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Страница 721: ...Rev 3 0 10 02 page 663 of 686 ø A23 to A0 to tBRQS tBACD tBZD tBACD tBZD tBRQS Figure 24 11 External Bus Release Timing ...
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