Hitachi H8S/2215 Series, Руководство по оборудованию

Страница: 317 / 745

Rev. 3.0, 10/02, page 259 of 686
Table 9.70 PF0 Pin Function
Operating Mode Modes 4 to 6 Mode 7
BRLE 0 1
−
PF0DDR 0 1
−
0 1
PF0 input PF0 output
BREQ
input PF0 input PF0 output Pin function
IRQ2
input *
Notes: * When used as an external interrupt input pin, do not use as an I/O pin for another function.
9.12 Port G
Port G is a 5-bit I/O port that also has functioning as external interrupt input (
IRQ7
).and bus
control output (
CS0
to
CS3
). The port G has the following registers.
•
Port G data direction register (PGDDR)
•
Port G data register (PGDR)
•
Port G register (PORTG)
9.12.1 Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G. If port G is, an
undefined value will be read.
Bit Bit Name Initial Value R/W Description
7 to
5
−
Undefined
−
Reserved
These bits are undefined and cannot be modified.
4 PG4DDR 0/1 * W
3 PG3DDR 0 W
2 PG2DDR 0 W
1 PG1DDR 0 W
0 PG0DDR 0 W
Modes 4 to 6:
Setting a PGDDR bit to 1 makes the PG4 to PG1 pins bus
control signal outputs, while clearing the bit to 0 makes
the pin input ports. signal outputs, while clearing the bit to
0 makes the pin input ports. Setting a PGDDR bit to 1
makes the PG0 pin an output port, while clearing the bit to
0 makes the pin an input port. PGDDR are ignored, and
port G pins automatically function as data.
Mode 7:
Setting a PGDDR bit to 1 makes the corresponding port G
pin an output port, while clearing the bit to 0 makes the
pin an input port.
Note:
*
In modes 4 to 6, set to 1; in mode 7 cleared to 0.