Hitachi H8S/2215 Series, Руководство по оборудованию

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Rev. 3.0, 10/02, page 383 of 686
13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer
rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and
performs internal synchronization. Receive data is latched internally at the rising edge of the 8th
pulse of the basic clock as shown in figure 13.6. Thus, the reception margin in asynchronous mode
is given by formula (1) below.
M = | (0.5 – ) – (L–0.5) F – ( 1+ F) | 100 [%] ... Formula (1)
2N
1
N
| D – 0.5 |
Where M: Reception margin
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 N (ratio
of bit rate to clock) in formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2
×
16)}
×
100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Internal basic
clock
16 clocks *
8 clocks
*
Receive data
(RxD)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 0 0 7
Note: * Figure 13.6 shows an example when the ABCS bit of SEMR0 is cleared to 0. When ABCS
is set to 1, the clock frequency of basic clock is 8 times the bit rate and the receive data is
sampled at the rising edge of the 4th pulse of the basic clock.
Figure 13.6 Receive Data Sampling Timing in Asynchronous Mode