RTMCSR—Refresh Timer Control/Status Register
H'AD
Refresh controller
Bit
Initial value
Read/Write
7
CMF
0
R/(W)
6
CMIE
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
0
—
1
—
2
—
1
—
1
—
1
—
Compare match flag
Compare match interrupt enable
0
[Clearing condition]
Read CMF when CMF = 1, then write 0 in CMF
1
[Setting condition]
RTCNT = RTCOR
Note: Only 0 can be written, to clear the flag.
*
0
The CMI interrupt requested by CMF is disabled
1
The CMI interrupt requested by CMF is enabled
Clock select 2 to 0
CKS2
Counter Clock Source
CKS1
Bit 4
CKS0
Bit 3
Bit 5
0
1
Clock input is disabled
ø/2
ø/8
ø/32
ø/128
ø/512
ø/2048
0
1
0
1
0
1
0
1
0
1
0
ø/4096
1
*
794
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