Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T
3
state of a general register read cycle, the value before input capture is read.
See figure 10-66.
Figure 10-66 Contention between General Register Read and Input Capture
ø
Address bus
Internal read signal
Input capture signal
GR
Internal data bus
GR address
X
General register read cycle
T
1
T
2
T
3
X
M
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