Table A-3 Number of States per Cycle
Access Conditions
External Device
8-Bit Bus
16-Bit Bus
On-Chip 8-Bit
16-Bit 2-State 3-State 2-State 3-State
Cycle
Memory
Bus
Bus
Access
Access
Access
Access
Instruction fetch
S
I
2
6
3
4
6 + 2m
2
3 + m
Branch address read
S
J
Stack operation
S
K
Byte data access
S
L
3
2
3 + m
Word data access
S
M
6
4
6 + 2m
Internal operation
S
N
1
Legend
m: Number of wait states inserted into external device access
On-Chip Sup-
porting Module
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