TCNT—Timer Counter
H'A9 (read),
WDT
H'A8 (write)
RSTCSR—Reset Control/Status Register
H'AB (read),
WDT
H'AA (write)
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Count value
Bit
Initial value
Read/Write
7
WRST
0
R/(W)
6
RSTOE
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Reset output enable
0
External output of reset signal is disabled
1
External output of reset signal is enabled
Watchdog timer reset
0
[Clearing condition]
• Reset signal input at RES pin
• When WRST= "1", write "0" after reading WRST flag
1
[Setting condition]
TCNT overflow generates a reset signal
Note: Only 0 can be written in bit 7, to clear the flag.
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