External Clock: The external clock frequency should be equal to the system clock frequency
(ø) when not divided by the on-chip frequency divider. Table 19-3, figures 19-6 and 19-7
indicate the clock timing.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by
the on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to
external devices after the external clock settling time (t
DEXT
) has passed after the clock input.
The system must remain reset with the reset signal low during t
DEXT
, while the clock output is
unstable.
Table 19-3 Clock Timing
V
CC
=
2.7 V to 5.5 V
V
CC
= 5.0 V ± 10%
Item
Symbol
Min
Max
Min
Max
Unit Test Conditions
External clock input t
EXL
40
—
20
—
ns
Figure 19-6
low pulse width
External clock input t
EXH
40
—
20
—
ns
high pulse width
External clock rise
t
EXr
—
10
—
5
ns
time
External clock fall
t
EXf
—
10
—
5
ns
time
Clock low pulse
t
CL
0.4
0.6
0.4
0.6
t
cyc
ø
≥
5 MHz
Figure
width
80
—
80
—
ns
ø < 5 MHz
21-7
Clock high pulse
t
CH
0.4
0.6
0.4
0.6
t
cyc
ø
≥
5 MHz
width
80
—
80
—
ns
ø < 5 MHz
External clock
t
DEXT
*
500
—
500
—
µs
Figure 19-7
output settling
delay time
Note:
*
t
DEXT
includes 10 t
cyc
of
RES
(t
RESW
).
637
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