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Field
Name
R/W
Description
1000: SYSCLK 2-divided frequency
1001: SYSCLK 4-divided frequency
1010: SYSCLK 8-divided frequency
1011: SYSCLK 16-divided frequency
1100: SYSCLK 64-divided frequency
1101: SYSCLK 128-divided frequency
1110: SYSCLK 256-divided frequency
1111: SYSCLK 512-divided frequency
Note: When the prescaler factor of AHB clock is greater than 1, the
prefetch buffer must be enabled.
10:8
APB1PSC
R/W
APB1 Clock Prescaler Factor Configure
Control the prescaler factor of low-speed APB1 clock (PCLK1)
0xx: No frequency division for HCLK
100: HCLK 2-divided frequency
101: HCLK 4-divided frequency
110: HCLK 8-divided frequency
111: HCLK 16-divided frequency
15:11
Reserved
16
PLLSRCSEL
R/W
PLL Clock Source Select
This bit can be changed only when PLL is disabled.
0: HSICLK is used as PLL clock source after 2 frequency division
1: HSECLK is used as PLL clock source
17
PLLHSEPSC
R/W
HSECLK Prescaler Factor for PLL Clock Source
Refer to Bit 0 of RCM_CFG2.
21:18
PLLMULCFG
R/W
PLL Multiplication Factor Configure
Determine PLL multiplication factor. This bit can be written only when
PLL is disabled.
0000: PLLCLK 2-multiple frequency output
0001: PLL 3-multiple frequency output
0010: PLL 4-multiple frequency output
0011: PLL 5-multiple frequency output
0100: PLL 6-multiple frequency output
0101: PLL 7-multiple frequency output
0110: PLL 8-multiple frequency output
0111: PLL 9-multiple frequency output
1000: PLL 10-multiple frequency output
1001: PLL 11-multiple frequency output
1010: PLL 12-multiple frequency output
1011: PLL 13-multiple frequency output
1100: PLL 14-multiple frequency output
1101: PLL 15-multiple frequency output
1110: PLL 16-multiple frequency output
1111: PLL 16-multiple frequency output
Note: The output frequency of PLL cannot be greater than 48MHz.
23:22
Reserved
