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Field
Name R/W
Description
15:0
CC1
R/W
Capture/Compare Channel 1 Value
When the capture/compare channel 1 is configured as input mode:
CC1 contains the counter value transmitted by the last input capture channel 1
event.
When the capture/compare channel 1 is configured as output mode:
CC1 contains the current load capture/compare register value
Compare the value CC1 of the capture and compare channel 1 with the value
CNT of the counter to generate the output signal on OC1.
When the output compare preload is disabled (OC1PEN=0 for TMRx_CCM1
register), the written value will immediately affect the output compare results;
If the output compare preload is enabled (OC1PEN=1 for TMRx_CCM1
register), the written value will affect the output compare result when an update
event is generated.
Break and dead-time register (TMRx_BDT)
Offset address: 0x44
Reset value: 0x0000
According to the lock setting, AOEN, BRKPOL, BRKEN, IMOS, RMOS and
DTS[7:0] bits all can be write-protected, and it is necessary to configure them
when writing to TMRx_BDT register for the first time.
Field
Name
R/W
Description
7:0
DTS
R/W
Dead Time Setup
DT is the dead duration, and the relationship between DT and register DTS
is as follows:
DTS[7:5]=0xx=>DT=DTS[7:0]×T
DTS
，
T
DTS
=T
DTS
；
DTS[7:5]=10x=>DT=
（
64+DTS[5:0])×T
DTS
，
T
DTS
=2×T
DTS
；
DTS[7:5]=110=>DT=
（
32+DTS[4:0])×T
DTS
，
T
DTS
=8×T
DTS
；
DTS[7:5]=111=>DT=
（
32+DTS[4:0]
）
×T
DTS
，
T
DTS
=16×T
DTS
；
For example: assuming T
DTS
=125ns (8MHZ), the dead time setting is as
follows:
If the step time is 125ns, the dead time can be set from 0 to 15875ns;
If the step time is 250ns, the dead time can be set from 16μs to 31750ns;
If the step time is 1μs, the dead time can be set from 32μs to 63μs;
If the step time is 2μs, the dead time can be set from 64μs to 126μs.
Note: Once LOCK level (LOCKCFG bit in TMRx_BDT register) is set to 1, 2
or 3, these bits cannot be modified.
9:8
LOCKCFG R/W
Lock Write Protection Mode Configure
00: Without Lock write protection level; the register can be written directly
01: Lock write protection level 1
It cannot be written to DTS, BRKEN, BRKPOL and AOEN bits of
TMRx_BDT, and OCxOIS and OCxNOIS bits of TMRx_CTRL2 register.
10: Lock write protection level 2
It is not allowed to write to all bits with protection level 1 and write to the
CCxPOL and OCxNPOL bits in TMRx_CCEN register and the RMOS
and IMOS bits in TMRx_BDT register.
11: Lock write protection level 3
It is not allowed to write to all bits with protection level 2, and write to the
OCxMOD and OCxPEN bits of TMRx_CCMx register.
Note: After system reset, the lock write protect bit can only be written once.
10
IMOS
R/W
Idle Mode Off-state Configure
Idle mode means MOEN=0; disable means CcxEN=0; this bit describes
the impact of different values for this bit on the output waveform when
MOEN=0 and CcxEN changes from 0 to 1.
0: OCx/OCxN output is disabled
1: If CCxEN=1, the invalid level is output during the dead time (the specific
level value is affected by the polarity configuration), and the idle level is
