Geehy SEMICONDUCTOR APM32F030x4x6x8xC, Руководство пользователя

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22.5.3.2
Requirements for I2C clock
（
1
）
t
I2C_CLK
< (t
low
-t
filters
)/4 and t
I2C_CLK
<t
HIGH
（
2
）
t
low
: SCL low-level time
（
3
）
t
HIGH
: SCL high-level time
（
4
）
t
filters
: Total lag caused by analog filter and digital filter when I2C is started
I2C clock configuration
Before peripherals are started, it is required to configure SCLH and SCLL bits in
I2C_TIMING register to configure the I2C clock.
It can realize clock synchronization mechanism and support multiple master
environments and slave clock extension.
t
SCL
=t
SYNC1
+t
SYNC2
+{
（（
SCLH+1
）
+
（
SCLL+1
））
*
（
TI1
）
* t
I2C_CLK
}
t
SYNC1
depends on:
 SCL descending slope
 Input delay of analog filter
 Input delay of digital filter
 Delay caused by synchronous I2C_CLK clock of SCL
t
SYNC2
depends on:
 SCL rising slope:
 Input delay of analog filter
 Input delay of digital filter
 Delay caused by synchronous I2C_CLK clock of SCL
To make I2C compatible with SMBus mode, the requirements for clock timing are
shown in the table below:
Table 71 Clock Timing Requirement
Symbol Parameter
Standard mode Fast mode Fast mode plus SMBus
Unit
Min Max Min Max Min Max Min Max
f
SCL
SCL clock
frequency
-
100
-
400
-
1000
-
100 KHz
t
HD:STA
START
signal hold
time
4
-
0.6
-
0.26
-
4.0
-
μs
t
SU:STA
START
signal
setup time
5
-
0.6
-
0.26
-
4.7
-
μs
t
SU:STO
STOP
signal
setup time
4
-
0.6
-
0.26
-
4.7
-
μs
t
BUF
Idle time of
bus
between
STOP and
START
signals
5
-
1.3
-
0.50
-
4.0
-
μs
t
LOW
SCL clock
low-level
time
8
-
1.3
-
0.50
-
4.7
-
μs
t
HIGH
SCL clock
high-level
time
4
-
0.6
-
0.26
-
4.0 50
μs