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This peripheral can be supported by SMBus reminder signal. When a device that
is used only as the slave wants to initiate communication, it can notify HOST
through SMBALERT pin. HOST will handle the interrupt and then access all
SMBALERTdevices through the reminder response address (0b0001100). Only
the device with the SMBALERT pin pulled down will respond to the reminder
response address.
SMBus timeout management
Table 73 SMBus Timeout Specification
Symbol
Parameter
Range
Unit
Min
Max
t
TIMEOUT
Low timeout of detection clock
25
35
ms
t
LOW:SEXT
Low extension time of cumulative clock of slave
-
25
ms
t
LOW:MEXT
Low extension time of cumulative clock of master
-
10
ms
t
LOW:SEXT
is an extensible clock cycle accumulation given by a slave device from
START to STOP. When a slave device or a master device occupies the clock,
the total low clock time is greater than t
LOW:SEXT
. Therefore, the test condition
of this parameter is that the slave is the only communication target of a
full-speed master.
t
LOW:MEXT
is the clock cycle accumulation allowed by a master device to send a byte in
the way of from START to ACK, from ACK to ACK, from ACK to STOP. When
another slave device or master occupies the clock, the total time occupies by
the clock may also be greater than t
LOW:MEXT
. Therefore, the measurement
condition of this parameter is that only one full-speed slave is the only
communication target.
Figure 106 t
LOW:SEXT
and t
LOW:MEXT
Time
START
STOP
t
L OW : SE X T
t
L OW : ME X T
t
L OW : ME X T
t
LOW:MEXT
22.5.4.4
Error flag bit
I2C communication has the following error flag bits that may cause
communication failure.
Bus error flag bit (BERRFLG)
When a START or STOP condition is detected outside 9 times of SCL clock
pulse signal, a bus error will occur. When SCL is high and a rising or falling edge
