Freescale Semiconductor MC9S12ZVHL32, Справочное руководство

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S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 675
Chapter 20
ECC Generation module (SRAM_ECCV1)
20.1 Introduction
The purpose of ECC logic is to detect and correct as much as possible memory data bit errors. These soft
errors can occur randomly during operation, mainly generated by alpha radiation. Soft Error means, that
only the information inside the memory cell is corrupt, the memory cell itself is not damaged. A write
access with correct data solves the issue. If the ECC algorithm is able to correct the data, then the system
can use this corrected data without any issues. If the ECC algorithm is able to detect, but not correct the
error, then the system is able to ignore the memory read data to avoid system malfunction.
The ECC value is calculated based on an aligned 2 byte memory data word. The ECC algorithm is able to
detect and correct single bit ECC errors. Double bit ECC errors will be detected but the system is not able
to correct these errors. This kind of ECC code is called SECDED code. This ECC code requires 6
additional parity bits for each 2 byte data word.
20.1.1 Features
The SRAM_ECC module provides the ECC logic for the system memory based on a SECDED algorithm.
Main features of the SRAM_ECC module:
• SECDED ECC code
– single bit error detection and correction per 2 byte data word
– double bit error detection per 2 byte data word
• memory initialization function
• byte wide system memory write access
• automatic single bit ECC error correction for read and write accesses
• debug logic to read and write raw use data and ECC values
20.2 Memory Map and Register Definition
This section provides a detailed description of all memory and registers for the SRAM_ECC module.
20.2.1
Register Summary
Figure 20-1 shows the summary of all implemented registers inside the SRAM_ECC module.