Freescale Semiconductor MC9S12ZVHL32, Справочное руководство

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Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 147
Table 5-5. BDCCSRH Field Descriptions
Field Description
7
ENBDC
Enable BDC — This bit controls whether the BDC is enabled or disabled. When enabled, active BDM can be
entered and non-intrusive commands can be carried out. When disabled, active BDM is not possible and the
valid command set is restricted. Further information is provided in
Table 5-7 .
0 BDC disabled
1 BDC enabled
Note: ENBDC is set out of reset in special single chip mode.
6
BDMACT
BDM Active Status — This bit becomes set upon entering active BDM. BDMACT is cleared as part of the active
BDM exit sequence.
0 BDM not active
1 BDM active
Note: BDMACT is set out of reset in special single chip mode.
5
BDCCIS
BDC Continue In Stop — If ENBDC is set then BDCCIS selects the type of BDC operation in stop mode (as
shown in Table 5-3 ). If ENBDC is clear, then the BDC has no effect on stop mode and no BDC communication
is possible.If ACK pulse handshaking is enabled, then the first ACK pulse following stop mode entry is a long
ACK. This bit cannot be written when the device is in stop mode.
0 Only the BDCCLK clock continues in stop mode
1 All clocks continue in stop mode
3
STEAL
Steal enabled with ACK — This bit forces immediate internal accesses with the ACK handshaking protocol
enabled. If ACK handshaking is disabled then BDC accesses steal the next bus cycle.
0 If ACK is enabled then BDC accesses await a free cycle, with a timeout of 512 cycles
1 If ACK is enabled then BDC accesses are carried out in the next bus cycle
2
CLKSW
Clock Switch — The CLKSW bit controls the BDCSI clock source. This bit is initialized to “0” by each reset and
can be written to “1”. Once it has been set, it can only be cleared by a reset. When setting CLKSW a minimum
delay of 150 cycles at the initial clock speed must elapse before the next command can be sent. This guarantees
that the start of the next BDC command uses the new clock for timing subsequent BDC communications.
0 BDCCLK used as BDCSI clock source
1 Device fast clock used as BDCSI clock source
Note: Refer to the device specification to determine which clock connects to the BDCCLK and fast clock inputs.
1
UNSEC
Unsecure — If the device is unsecure, the UNSEC bit is set automatically.
0 Device is secure.
1 Device is unsecure.
Note: When UNSEC is set, the device is unsecure and the state of the secure bits in the on-chip Flash EEPROM
can be changed.
0
ERASE
Erase Flash — This bit can only be set by the dedicated ERASE_FLASH command. ERASE is unaffected by
write accesses to BDCCSR. ERASE is cleared either when the mass erase sequence is completed, independent
of the actual status of the flash array or by a soft reset.
Reading this bit indicates the status of the requested mass erase sequence.
0 No flash mass erase sequence pending completion
1 Flash mass erase sequence pending completion.