Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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Freescale Semiconductor
10.8.7
Conversion flow control application information
The ADC12B_LBA provides various conversion control scenarios to the user accomplished by the
following features.
The ADC conversion flow control can be realized via the data bus only, the internal interface only, or by
both access methods. The method used is software configurable via bits ACC_CFG[1:0].
The conversion flow is controlled via the four conversion flow control bits: SEQA, TRIG, RSTA, and
LDOK.
Two different conversion flow control modes can be configured: Trigger Mode or Restart Mode
Single or double buffer configuration of CSL and RVL.
10.8.7.1
Initial Start of a Command Sequence List
At the initial start of a Command Sequence List after device reset all entries for at least one of the two CSL
must have been completed and data must be valid. Depending on if the CSL_0 or the CSL_1 should be
executed at the initial start of a Command Sequence List the following conversion control sequence must
be applied:
If CSL_0 should be executed at the initial conversion start after device reset:
A Restart Event and a Trigger Event must occur (depending to the selected conversion flow control mode
the events must occur one after the other or simultaneously) which causes the ADC to start conversion with
commands loaded from CSL_0.
If CSL_1 should be executed at the initial conversion start after device reset:
Bit LDOK must be set simultaneously with the Restart Event followed by a Trigger Event (depending on
the selected conversion flow control mode the Trigger events must occur simultaneously or after the
Restart Event is finished). As soon as the Trigger Event gets executed the ADC starts conversion with
commands loaded from CSL_1.
As soon as a new valid Restart Event occurs the flow for ADC register load at conversion sequence start
as described in
Section 10.5.3.3, “ADC List Usage and Conversion/Conversion Sequence Flow
10.8.7.2
Restart CSL execution with currently active CSL
To restart a Command Sequence List execution it is mandatory that the ADC is idle (no conversion or
conversion sequence is ongoing).
If necessary, a possible ongoing conversion sequence can be aborted by the Sequence Abort Event (setting
bit SEQA). As soon as bit SEQA is cleared by the ADC, the current conversion sequence has been aborted
and the ADC is idle (no conversion sequence or conversion ongoing).
After a conversion sequence abort is executed it is mandatory to request a Restart Event (bit RSTA set).
After the Restart Event is finished (bit RSTA is cleared), the ADC accepts a new Trigger Event (bit TRIG
can be set) and begins conversion from the top of the currently active CSL. In conversion flow control
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