Freescale Semiconductor MC9S12ZVHL32, Справочное руководство

Страница: 615 / 874

Chapter 16 Motor Controller (MC10B8CV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 615
value, DUTY, contained in D[10:1] in MCDCx. When a match (output compare between motor controller
timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a
logic high level until the motor controller timer counter overflows (reaches the value defined by
P[10:1] – 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM output will
return to a logic low level. This completes the first half of the PWM period. During the second half of the
PWM period, the PWM output will remain at a logic low level until either the motor controller timer
counter matches the 10-bit PWM duty cycle value, DUTY, contained in D[10:1] in MCDCx if D0 = 0, or
the motor controller timer counter matches the 10-bit PWM duty cycle value + 1 (the value of D[10:1] in
MCDCx is increment by 1 and is compared with the motor controller timer counter value) if D0 = 1 in the
corresponding duty cycle register. When a match occurs, the PWM output will toggle to a logic high level
and will remain at a logic high level until the motor controller timer counter overflows (reaches the value
defined by P[10:1] – 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM
output will return to a logic low level.
This process will repeat every number of counts of the motor controller timer counter defined by the period
register contents (P[10:0]). If the output is neither set to 0% nor to 100% there will be four edges on the
PWM output per PWM period in this case. Therefore, the PWM output compare function will alternate
between DUTY and DUTY + 1 every half PWM period if D0 in the corresponding duty cycle register is
set to 1. The relationship between the motor controller timer counter clock (f
TC
), motor controller timer
counter value, and left aligned PWM output if DITH = 1 is shown in Figure 16-18 and Figure 16-19 .
Figure 16-20 and Figure 16-21 show right aligned and center aligned PWM operation respectively, with
dither feature enabled and D0 = 1. Please note: In the following examples, the MCPER value is defined
by the bits P[10:0], which is, if DITH = 1, always an even number.
NOTE
The DITH bit must be changed only if the motor controller is disabled (all
channels disabled or period register cleared) to avoid erroneous waveforms.
Figure 16-18. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 31, MCPER = 200, RECIRC = 0
0 15
PWM Output
16 0
100 Counts
Motor Controller
Timer Counter
Motor Controller
Timer Counter
Clock
0 16
1 Period
100 Counts
15 99
99