Freescale Semiconductor MC9S12ZVHL32, Справочное руководство

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Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
210 Freescale Semiconductor
When using the AB comparator pair for a range comparison, the data bus can be used for qualification by
using the comparator A data and data mask registers. Similarly when using the CD comparator pair for a
range comparison, the data bus can be used for qualification by using the comparator C data and data mask
registers. The DBGACTL/DBGCCTL RW and RWE bits can be used to qualify the range comparison on
either a read or a write access. The corresponding DBGBCTL/DBGDCTL bits are ignored. The
DBGACTL/DBGCCTL COMPE/INST bits are used for range comparisons. The DBGBCTL/DBGDCTL
COMPE/INST bits are ignored in range modes.
6.4.2.4.1 Inside Range (CompAC_Addr

address

CompBD_Addr)
In the Inside Range comparator mode, either comparator pair A and B or comparator pair C and D can be
configured for range comparisons by the control register (DBGC2). The match condition requires a
simultaneous valid match for both comparators. A match condition on only one comparator is not valid.
6.4.2.4.2 Outside Range (address < CompAC_Addr or address > CompBD_Addr)
In the Outside Range comparator mode, either comparator pair A and B or comparator pair C and D can
be configured for range comparisons. A single match condition on either of the comparators is recognized
as valid. Outside range mode in combination with opcode address matches can be used to detect if opcodes
are from an unexpected range.
NOTE
When configured for data access matches, an outside range match would
typically occur at any interrupt vector fetch or register access. This can be
avoided by setting the upper or lower range limit to $FFFFFF or $000000
respectively. Interrupt vector fetches do not cause opcode address matches.
6.4.3 Events
Events are used as qualifiers for a state sequencer change of state. The state control register for the current
state determines the next state for each event. An event can immediately initiate a transition to the next
state sequencer state whereby the corresponding flag in DBGSR is set.
6.4.3.1 Comparator Match Events
6.4.3.1.1 Opcode Address Comparator Match
The comparator is loaded with the address of the selected instruction and the comparator control register
INST bit is set. When the opcode reaches the execution stage of the instruction queue a match occurs just
before the instruction executes, allowing a breakpoint immediately before the instruction boundary. The
comparator address register must contain the address of the first opcode byte for the match to occur.
Opcode address matches are data independent thus the RWE and RW bits are ignored. CPU compares are
disabled when BDM becomes active.