Freescale Semiconductor MC9S12ZVHL32, Справочное руководство

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Chapter 16 Motor Controller (MC10B8CV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
614 Freescale Semiconductor
16.4.1.3.5 Dither Bit (DITH)
The purpose of the dither mode is to increase the minimum length of output pulses without decreasing the
PWM resolution, in order to limit the pulse distortion introduced by the slew rate control of the outputs. If
dither mode is selected the output pattern will repeat after two timer counter overflows. For the same
output frequency, the shortest output pulse will have twice the length while dither feature is selected. To
achieve the same output frame frequency, the prescaler of the MC10B8C module has to be set to twice the
division rate if dither mode is selected; e.g., with the same prescaler division rate the repeat rate of the
output pattern is the same as well as the shortest output pulse with or without dither mode selected.
The DITH bit in control register 0 enables or disables the dither function.
DITH = 0: dither function is disabled.
When DITH is cleared and assuming left aligned operation and RECIRC = 0, the PWM output will start
at a logic low level at the beginning of the PWM period (motor controller timer counter = 0x000). The
PWM output remains low until the motor controller timer counter matches the 11-bit PWM duty cycle
value, DUTY, contained in D[10:0] in MCDCx. When a match (output compare between motor controller
timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a
logic high level until the motor controller timer counter overflows (reaches the contents of MCPER – 1).
After the motor controller timer counter resets to 0x000, the PWM output will return to a logic low level.
This completes one PWM period. The PWM period repeats every P counts (as defined by the bits P[10:0]
in the motor controller period register) of the motor controller timer counter. If DUTY >= P, the output
will be static low. If DUTY = 0x0000, the output will be continuously at a logic high level. The
relationship between the motor controller timer counter clock, motor controller timer counter value, and
PWM output while DITH = 0 is shown in
Figure 16-17 .
Figure 16-17. PWM Output: DITH = 0, MCAM[1:0] = 01, MCDC = 100,
MCPER = 200, RECIRC = 0
DITH = 1: dither function is enabled
Please note if DITH = 1, the bit P0 in the motor controller period register will be internally forced to 0 and
read always as 0.
When DITH is set and assuming left aligned operation and RECIRC = 0, the PWM output will start at a
logic low level at the beginning of the PWM period (when the motor controller timer counter = 0x000).
The PWM output remains low until the motor controller timer counter matches the 10-bit PWM duty cycle
0 100 0 100 0
PWM Output
1 Period
200 Counts 200 Counts
1 Period
Motor Controller
Timer Counter Clock
Motor Controller
Timer Counter
199 199