Epson S1C6S3N2, Техническое руководство

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S1C6S3N2 TECHNICAL HARDWARE
EPSON
I-73
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)
Event Counter
The S1C6S3N2 Series has an event counter that counts the
clock signals input from outside.
The event counter is configured of eight-bit binary counters
(UP counters). The clock pulses are input through K10 pin
or K03 pin of the input port. (K03 input can be selected by
mask option.)
Figure 4.10.1 shows the configuration of the event counter.
4.10
Configuration of
event counter
Operation of event
counter
The clock signal input from terminal K10 is input to the
event counter via the noise rejector. (Either K10 or K03 can
be selected as the event counter input by mask option.)
The event counter increments when the clock signal is
input, and the incremented data can be read out through
the software.
RUN and STOP of the event counter are performed by mak-
ing the clock of the noise rejector ON and OFF. This is
controlled by writing data to the EVRUN register.
The counter counts up at the rising edge of the K10 input
clock or the falling edge of the K03 input clock.
Figure 4.10.2 is the timing chart for the event counter.
Input of K10 terminal
EVRUN
Input of event counter
Defined time
T
ON2
T
OFF
T
N
Noise
STOP
T
ON
T
STP
T
ON
T
OFF
T
N
T
STP
T
ON2
≥
1.5 T
CH
≥
1.0 T
CH
<
0.5 T
CH
≥
0.5 T
CH
≥
1.5 T
CH
+ T
STP
(Execution time)
T
CH
= 1/f
CH
Through the mask option, f
CH
selects f
OSC1
/16 or f
OSC1
/128
for the clock frequency of the
noise rejector
RUN
Fig. 4.10.2
Timing chart of
event counter
Noise rejector
circuit
Input port
K10
Event counter
[EV00–EV07]
Interrupt request
Data bus
Event counter RUN/STOP
Event counter reset
Fig. 4.10.1
Configuration of
event counter