Epson S1C6S3N2, Техническое руководство

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S1C6S3N2 TECHNICAL HARDWARE
EPSON
I-33
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Interrupt mask register Differential register
EIK03 EIK02 EIK01 EIK00 DFK03 DFK02 DFK01 DFK00
1 1 1 0 1 0 1 0
With the above setting, the interrupt for K00–K03 occurs in
the following conditions.
Input port
(1) K03 K02 K01 K00
1 0 1 0
(Initial value)
(2) K03 K02 K01 K00
1 0 1 1
(3) K03 K02 K01 K00
0 0 1 1
→
Interrupt generated
(4) K03 K02 K01 K00
0 1 1 1
↓
↓
K00 is masked, so the three bits
of K01–K03 cease matching
those of the differential register
DFK01–DFK03, and an inter-
rupt occurs.
↓
K00 is masked by the interrupt mask register (EIK00), so
that an interrupt does not occur at (2). At (3), K03 changes
to "0"; the data of the terminal that is interrupt enabled no
longer matches the data of the differential register, so that
interrupt occurs. As already explained, the condition for the
interrupt to occur is the change in the port data and con-
tents of the differential register from matching to
nonmatching. Hence, in (4), when the nonmatching status
changes to another nonmatching status, an interrupt does
not occur. Further, terminals that have been masked for
interrupt do not affect the conditions for interrupt genera-
tion.
Fig. 4.4.3
Example of interrupt of
K00–K03