I-90
EPSON
S1C6S3N2 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.13.1 shows the factors for generating interrupt
requests.
The interrupt flags are set to "1" depending on the corre-
sponding interrupt factors.
The CPU operation is interrupted when any of the conditions
below set an interrupt factor flag to "1".
• The corresponding mask register is "1" (enabled)
• The interrupt flag is "1" (EI)
The interrupt factor flag is a read-only register, but can be
reset to "0" when the register data is read out.
At initial reset, the interrupt factor flags are reset to "0".
Reading of interrupt factor flags is available at EI, but be careful in
the following cases.
If the interrupt mask register value corresponding to the interrupt
factor flags to be read is set to "1", an interrupt request will be
generated by the interrupt factor flags set timing, or an interrupt
request will not be generated.
Be very careful when interrupt factor flags are in the same address.
Interrupt factors
Note
Interrupt Factor
Interrupt Factor Flag
Clock timer 2 Hz falling edge
TI2
(079H·D2)
Clock timer 8 Hz falling edge
TI8
(079H·D1)
Clock timer 32 Hz falling edge
TI32
(079H·D0)
Stopwatch counter
SWIT1
1 Hz falling edge
(07AH·D1)
Stopwatch counter
SWIT0
10 Hz falling edge
(07AH·D0)
Input data (K00–K03)
IK0
Rising or falling edge
(07AH·D2)
Input data (K10)
IK1
Rising or falling edge
(07AH·D3)
Table 4.13.1
Interrupt factors
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