Epson S1C6S3N2, Техническое руководство

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I-16
EPSON
S1C6S3N2 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER 4
Fig. 4.1.1
Memory map (page 0)
PERIPHERAL CIRCUITS AND
OPERATION
Peripheral circuits (timer, I/O, and so on) of the S1C6S3N2
Series are memory mapped, and interfaced with the CPU.
Thus, all the peripheral circuits can be controlled by using
the memory operation command to access the I/O data
memory in the memory map.
The following sections describe how the peripheral circuits
operation.
Memory Map
Data memory of the S1C6S3N2 Series has an address space
of 160 words, of which 48 words are allocated to segment
data memory and 32 words to I/O data memory.
Figures 4.1.1 and 4.1.2 present the overall memory maps of
the S1C6S3N2 Series, and Tables 4.1.1(a)–4.1.1(f) the pe-
ripheral circuits' (I/O space) memory maps.
4.1
Address
Page High
Low
0 1 2 3 4 5 6 7 8 9 A B C D E F
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
RAM (112 words x 4 bits)
R/W
RAM (32 words x 4 bits)
R/W
I/O data memory Tables 4.1.1(a)–4.1.1(d)
Unused area
I/O data memory Tables 4.1.1(e)–4.1.1(f)