26 LCD CONTROLLER (LCDC)
26-22
Seiko Epson Corporation
S1C33L26 TECHNICAL MANUAL
5.6.3 Relationship between 4-bpp Pixel Data and FPDAT Signals
Table 26.
Pixel data
FPDAT0/4/6/10
/11/15 signals
FPDAT3/5/9/14
signals
FPDAT2/8/13
signals
FPDAT1/7/12
signals
FPDAT[23:16]
signals
0xf
High (1)
High (1)
High (1)
High (1)
Low (0)
0xe
High (1)
High (1)
High (1)
Low (0)
Low (0)
0xd
High (1)
High (1)
Low (0)
High (1)
Low (0)
0xc
High (1)
High (1)
Low (0)
Low (0)
Low (0)
0xb
High (1)
Low (0)
High (1)
High (1)
Low (0)
0xa
High (1)
Low (0)
High (1)
Low (0)
Low (0)
0x9
High (1)
Low (0)
Low (0)
High (1)
Low (0)
0x8
High (1)
Low (0)
Low (0)
Low (0)
Low (0)
0x7
Low (0)
High (1)
High (1)
High (1)
Low (0)
0x6
Low (0)
High (1)
High (1)
Low (0)
Low (0)
0x5
Low (0)
High (1)
Low (0)
High (1)
Low (0)
0x4
Low (0)
High (1)
Low (0)
Low (0)
Low (0)
0x3
Low (0)
Low (0)
High (1)
High (1)
Low (0)
0x2
Low (0)
Low (0)
High (1)
Low (0)
Low (0)
0x1
Low (0)
Low (0)
Low (0)
High (1)
Low (0)
0x0
Low (0)
Low (0)
Low (0)
Low (0)
Low (0)
8-bpp mode (TFT panel, LUT bypassed)
To ensure a uniform brightness, R2–R0, G2–G0, and B1–B0 are connected to the TFT panel RGB signals
repeatedly.
B0
LCDC signals
0
8-bpp pixel data
TFT panel
R signals
FPD
AT23
FPD
AT22
FPD
AT21
FPD
AT20
FPD
AT19
FPD
AT18
FPD
AT17
FPD
AT16
FPD
AT15
FPD
AT14
FPD
AT13
FPD
AT12
FPD
AT11
FPD
AT10
FPD
AT
9
FPD
AT
8
FPD
AT
7
FPD
AT
6
FPD
AT
5
FPD
AT
4
FPD
AT
3
FPD
AT
2
FPD
AT
1
FPD
AT
0
TFT panel
G signals
TFT panel
B signals
B1
G0
G1
G2
R0
R1
R2
5.6.4 FPDAT Signals in LUT Bypass Mode (TFT panel, 8-bpp mode)
Figure 26.
When a pixel data is 0x59 (R = 0x2, G = 0x6, B = 0x1), for example, the FPDAT signals will be configured
as follows:
FPDAT15 = Low (0)
FPDAT10 = High (1)
FPDAT4 = Low (0)
FPDAT14 = High (1)
FPDAT9 = High (1)
FPDAT3 = High (1)
FPDAT13 = Low (0)
FPDAT8 = Low (0)
FPDAT2 = Low (0)
FPDAT12 = Low (0)
FPDAT7 = High (1)
FPDAT1 = High (1)
FPDAT11 = High (1)
FPDAT6 = High (1)
FPDAT0 = Low (0)
FPDAT5 = Low (0)
FPDAT[23:16] = Low (0)