18 UNIVERSAL SERIAL INTERFACE (USI)
18-24
Seiko Epson Corporation
S1C33L26 TECHNICAL MANUAL
Address
Register name
Function
0x300470
USI_ISTG
USI I
2
C Slave Mode Trigger Register
Starts I
2
C slave operations.
0x300471
USI_ISIE
USI I
2
C Slave Mode Interrupt Enable Register
Enables interrupts.
0x300472
USI_ISIF
USI I
2
C Slave Mode Interrupt Flag Register
Indicates interrupt occurrence status.
The USI registers are described in detail below. These are 8-bit registers.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
USI Global Configuration Register (USI_GCFG)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Global
Configuration
Register
(USI_GCFG)
0x300400
(8 bits)
D7–4 –
reserved
–
–
–
0 when being read.
D3
LSBFST
MSB/LSB first mode select
1 MSB first
0 LSB first
0
R/W
D2–0 USIMOD
[2:0]
Interface mode configuration
USIMOD[2:0]
I/F mode
0x0 R/W
0x7–0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
I
2
C slave
I
2
C master
SPI slave
SPI master
UART
Software reset
Note: This register must be configured before setting other USI registers.
D[7:4]
Reserved
D3
LSBFST: MSB/LSB First Mode Select Bit
Selects whether serial data will be transferred from the MSB or LSB.
1 (R/W): MSB first
0 (R/W): LSB first (default)
This setting affects all interface modes.
D[2:0]
USIMOD[2:0]: Interface Mode Configuration Bits
Selects an interface mode.
8.2 Interface Mode Selection
Table 18.
USIMOD[2:0]
Interface mode
0x5
I
2
C slave
0x4
I
2
C master
0x3
SPI slave
0x2
SPI master
0x1
UART
0x0
Software reset
(Default: 0x0)
Perform software reset (set USIMOD[2:0] to 0x0) and then set the interface mode before changing
other USI configurations.
USI Transmit Data Buffer Register (USI_TD)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI
Transmit Data
Buffer Register
(USI_TD)
0x300401
(8 bits)
D7–0 TD[7:0]
USI transmit data buffer
TD7 = MSB
TD0 = LSB
0x0 to 0xff
0x0 R/W
D[7:0]
TD[7:0]: USI Transmit Data Buffer Bits
Sets transmit data to be written to the transmit data buffer. (Default: 0x0)
In UART and SPI master modes, transmission begins immediately after writing data to this register. In
SPI slave mode, transmission will begin when the clock is input from the SPI master device.
In I
2
C master/slave mode, transmission begins by the software trigger for data transmission.
The data written to this register is converted into serial data through the shift register and is output from
the USI_DO pin with the bit set to 1 as high level and the bit set to 0 as low level.