Epson DLQ-3000 Minerva+, Руководство по обслуживанию, Страница: 39 / 189

Product Description
Rev. A
1-31
Reverse Channel
‰
Transmission mode IEEE-1284 nibble mode
‰
Adaptable connector Same as for the forward channel
‰
Synchronization Refer to the IEEE-1284 specification
‰
Handshaking Refer to the IEEE-1284 specification
‰
Data transmission timing Refer to the IEEE-1284 specification
‰
Signal level IEEE-1284 level 1 device
See the forward channel.
Table 1-26 shows the connector pin assignment and signals for reverse channel of the
parallel interface.
Table 1-26. Connector Pin Assignment and Signals (Reverse Channel)
Pin No. Signal Name
Return
GND Pin
I/O Description
1 HostClk 19 I Clock signal from the host computer.
2-9 DATA 1-8 20-27 I
These signals represent parallel data
on bits 2 to 9. Each signal is High
when the data is logical 1 and LOW
when the data is logical 0.
10 PtrClk 28 O Clock signal from the printer
11
PtrBusy /
Data bit 3,7
29 O
Busy signal from the printer.
Data bit 3 or 7 in reverse channel.
12
AckDatareq /
Data Bit 2,6
28 O
Acknowledge request signal.
Data bit 2 or 6 in reverse channel.
13 Xflag/Data bit
1,5 28 O
X flag signal.
Data bit 1 or 5 in reverse channel.
14 HostBusy 30 I Busy signal from the host computer
31 /INIT 30 I Not used
32
/Data Avail /
Data bit 0,4
29 O
Data available signal.
Data bit 0 or 4 in reverse channel.
36 1284-Active 30 I 1284 active signal.
18 Logic-H

O
Pulled up to +5V via 3.9 K-ohm
resistor.
35 +5V

O
Pulled up to +5V via 3.3 K-ohm
resistor.
17 Chassis GND
 
Chassis ground for the printer.
16,33,
19-30
GND
 
Signal ground.
15,34 NC
 
Not connected.
Note)
1. */* at the beginning of a signal means active low.
2. The I/O column indicates the direction of the signal as viewed form the printer.