Digital Equipment DECmpp 12000/Sx 100, Руководство по обслуживанию оборудования

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pe_macro(1)
exclusive OR of the shifted result with the starting data. If no corruption
occurred, the result is zero.
The test begins with a distance of zero (shifts to itself), and successively
widens the distance to a distance of 2047.
If an error occurs with any PE, the test prints an error message which gives
the distance shifted, the expected state of the error status bit and the actual
state of the error status bit (which, of course, is 1 or the message would not
have been printed in the first place).
•
onet1
: XNet Octagon Shift Test (with PMem activity) — Tests the ability of
the PEs to shift data around an octagon: north, northeast, east, southeast,
south, southwest, west and northwest. Each PE uses its own row, column
address as data and shifts it in each of the eight directions. After each shift,
the test performs several store operations to create extra activity in the
m-machine.
After the eight shifts, each PE does an exclusive OR of the shifted result with
the starting data. If no corruption occurred, the result is zero.
The test begins with a distance of zero (shifts to itself), and successively
widens the distance to a distance of 2047.
If an error occurs with any PE, the test prints an error message which gives
the distance shifted, the expected state of the error status bit and the actual
state of the error status bit (which, of course, is 1 or the message would not
have been printed in the first place).
•
ortest1
: Global OR And XOR Test — With all PEs enabled, each PE moves
data into PReg. Then all PEs perform a global OR of the PRegs into an ACU
register, the contents of which is checked for error.
Next, each PE uses the XOR function to invert all the bits of the data in
PReg. A global OR operation is then performed and result is checked for
error.
If an error occurs, the test prints an error message giving the operation
attempted, the PReg in question, the expected result and the actual result.
•
random1
: Random Macro Instruction Test — This test performs instructions
of all sizes and many types in random sequence. Occasionally, it checks
the contents of the CPSW status register for unexpected status. After each
instruction tested, it checks the results for error.
If an error occurs, it prints an error message giving the instruction under
test, the expected result and the actual result.
•
rt0a
: 16-Bit Router Send Test — Sets the e-bit and the t-bit for PE 0,0
only. Opens the router channel (to itself) and sends data using the router. It
checks the accuracy of the data and also checks that adjacent data remains
unchanged. This demonstrates not only that the data gets sent, but also that
only 16 bits are sent.
• rt0b : 16-Bit Router Fetch Test — Sets the e-bit and the t-bit for PE 0,0 only.
Opens the router channel (to itself) and fetches data using the router. It
checks the accuracy of the data and also checks that adjacent data remains
unchanged. This demonstrates not only that the data gets fetched, but also
that only 16 bits are fetched.
B–34 Data Parallel Unit Reference Pages