Digital Equipment DECmpp 12000/Sx 100, Руководство по обслуживанию оборудования

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pe_macro(1)
The test enables all the PEs. After each addition, the test performs a global
OR of each PE’s answer. If it detects an error, the test prints an error
message which gives the addition the test was attempting, the expected
answer and the actual answer.
After each addition, it performs a global OR of each PE’s flag bits. If any of
these is in error, an error message is printed giving the operation attempted,
the expected flag bits and the actual flag bits. The flag bits are collected as
shown:
2 1 0
n z v c
Overflow flag
Zero flag
Negative flag
bit 3
Carry flag
MPP_FIG_276
If this test reports a wrong answer, it indicates that the fault is associated
with one or more PEs.
•
AddTests3
: Check Flags After ADD And MOV Instructions — This test
executes a variety of additions and move instructions.
The test enables all the PEs and initializes their PRegs with an identical set
of data. After each operation, the test does a global OR of each PE’s answer,
then a global OR of each PE’s flag bits.
If it detects an error in the result, it prints an error message giving the
instruction under test, the expected result and the actual result. If any flag
is in error, the test prints an error message stating which flag is in error, the
expected value and the actual value.
• And1Tests1 : Single Bit AND Test — This is a test of the AND1 instruction.
It uses the following bits as operands:
Flag Bits PReg’s
lsb 2[c4] — where c4 = 1024
lflag 3[c4]
cflag 4[c4]
vflag 5[c4]
zflag 6[c4]
nflag 7[c4]
tflag 8[c4]
fflag 9[c4]
rflag 10[c4]
64[c0] 11[c4]
12[c4]
Data Parallel Unit Reference Pages B–17