pe_macro(1)
2
1
0
n
z
v
c
Overflow flag
Zero flag
Negative flag
bit
3
Carry flag
MPP_FIG_276
•
OrTests2
: Immediate To Register OR Test — This test performs 8-bit, 16-bit,
32-bit and 64-bit OR operations.
After each OR, if it detects an error, the test prints an error message which
gives the OR the test was attempting, the expected answer and the actual
answer.
After each OR, it checks the flag bits. If any of these is in error, an error
message is printed giving the operation attempted, the expected flag bits and
the actual flag bits. The flag bits are collected as shown:
2
1
0
n
z
v
c
Overflow flag
Zero flag
Negative flag
bit
3
Carry flag
MPP_FIG_276
•
ShiftTests
: Shift Instruction Test — Tests the four shift instructions:
shll: Logical shift left
shla: Arithmetic shift left
shrl: Logical shift right
shra: Arithmetic shift right
It performs 4-bit and 7-bit shifts, using a variety of operands:
Test #1 (message #1–#40): This test uses the value c1 = 4 to determine
how many places to shift the contents of 16[c0].
Test #2 (message #41–#80): This test uses the value c1 = 7 to determine
how many places to shift the contents of 16[c0].
Test #3 (message #81–#120): This test uses an immediate number in the
instruction to determine how many places to shift the contents of 16[c0].
Test #4 (message #121–#160): This test uses an immediate number in the
instruction to determine how many places to shift the contents of acc.
Test #5 (message #161–#180): This test uses the value 128[c0] = 4 to
determine how many places to shift the contents of 16[c0].
Test #6 (message #181–#200): This test uses the value acc = 4 to
determine how many places to shift the contents of 16[c0].
B–28 Data Parallel Unit Reference Pages
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