
pe_macro(1)
Test #7 (message #201–#240): This test uses the value in 128[c0] to
determine how many places to shift the contents of acc.
Test #8 (message #241–#260): This test uses the value 128[c0] = 7 to
determine how many places to shift the contents of 16[c0].
Test #9 (message #261–#280): This test uses the contents of acc to
determine how many places to shift the contents of 16[c0].
Test #10 (message #281–#300): This test uses the contents of 128[c0] to
determine how many places to shift the contents of acc.
Test #11 (message #301–#320): This test uses the contents of acc to
determine how many places to shift. It also shifts the contents of acc.
If the test detects an error, it prints an error message giving the attempted
operation, the expected results and the actual results.
•
SubTests1
: Register To Register SUBTRACTION Test — This test enables all
PEs and has them load data into PReg. Then it performs various 8-bit, 16-bit,
32-bit and 64-bit subtractions between PRegs.
After each SUBTRACTION, if it detects an error, the test prints an error
message which gives the SUBTRACTION the test was attempting, the
expected answer and the actual answer.
After each SUBTRACTION, it checks the flag bits. If any of these is in error,
the test prints an error message giving the operation attempted, the expected
flag bits and the actual flag bits. The flag bits are collected as shown:
2
1
0
n
z
v
c
Overflow flag
Zero flag
Negative flag
bit
3
Carry flag
MPP_FIG_276
•
SubTests2
: Immediate To Register SUBTRACTION Test — This test enables
all PEs, then performs various 8-bit, 16-bit, 32-bit and 64-bit subtractions
between immediate and PRegs.
After each SUBTRACTION, if it detects an error, the test prints an error
message which gives the SUBTRACTION the test was attempting, the
expected answer and the actual answer.
After each SUBTRACTION, it checks the flag bits. If any of these is in error,
the test prints an error message giving the operation attempted, the expected
flag bits and the actual flag bits. The flag bits are collected as shown:
2
1
0
n
z
v
c
Overflow flag
Zero flag
Negative flag
bit
3
Carry flag
MPP_FIG_276
Data Parallel Unit Reference Pages B–29
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