Serial Trigger and Decode
87
When the CS type is set to Clock Timeout, the clock idle time between frames is T3, the clock period is T1, then set
the timeout to a value between T1 and T3
Figure 10.12
Example 2
If the data width is set to be greater than 8 bits (such as 16 bits), the clock idle time between 8-bit data packets T2,
and then set the timeout time to a value between T1/2+T2 and T3.
Figure 10.13
Example 3
Содержание 2560B Series
Страница 1: ......
Страница 51: ...Digital Channels 51 Figure 8 9 Digital Bus...
Страница 127: ...Serial Trigger and Decode 127 Figure 10 63 Manchester Bus...
Страница 168: ...Reference Waveform 168 Figure 14 1 Recall REFB...
Страница 210: ...Save Recall 210 Figure 22 4 Save As...
